ARM cortex-M memory architecture

Index: ARM cortex-M relative study


load-store architecture :

- 大部分 RISC 都是屬於 load-store architecture, 資料先從 memory load 到 registers,
   ALU 運算都是用 registers, 之後再 store 回 memory

- 相對架構是 register memory architecture , 如 IBM360, Intel x86

Ref: http://www.cnblogs.com/amanlikethis/p/3380139.html



- Load-Store Architecture

- Register Memory Architecture

- Register-Plus-Memory Architecture



Cortex-M3 memory map
Ref: Hackpad

16 visible registers : R0~R12, SP, LR, PC

- banked stack pointer : only one is used for SP at a time.

- Stack limit register

Ref: ARM : white paper Architecture Technical Overview

v8m :
- Hardware divide instructions
- 16-bit immediate data handling instructions (MOVW, MOVT)
- Load acquire, store release instructions (C11 atomic variable handling)
- Trustzone
   * a new instruction called TT (Test Target) is introduced.
   * SAU / IDAU - SG/BLXNS / BXNS
   * stack limit
- MPU


v8m advantage

- application level security

- privilege level security

- Trustzone

- Anti-tampering

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ARM v8m memory type definition

- Normal memory

  ( 一般 記憶體 )

  ( 可做 cache )

- Device Memory

   ( 寫 1 清 0 的, 特殊程序的, counter, ... )

   ( 不可做 cache )

• G or nG – Gathering or non-Gathering. Multiple accesses to a device can be merged into a single transaction except for operations with memory ordering semantics, for example, memory barrier instructions, load acquire/store release.
• R or nR – Reordering or Non-reordering.
• E or nE – Early Write Acknowledge (similar to bufferable).

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